Curriculum Vita

J. KELLY FLANAGAN

Information Technology Vice President/CIO and
Professor of Computer Science
Brigham Young University
Provo, UT 84602
Office: 801-422-3142
Email: kelly_flanagan@byu.edu
Web: kelly.flanagan.io

EDUCATION

Ph.D., August 1993, Brigham Young University, Electrical and Computer Engineering.
Dissertation: A New Methodology for Accurate Trace Collection and Its Application to Memory Hierarchy Performance Modeling.

M.S., August 1989, Brigham Young University, Electrical Engineering.
Thesis: Processor Design Using Path Programmable Logic.

B.S., April 1988, Brigham Young University, Electrical Engineering.

ADMINISTRATIVE EXPERIENCE

 Chief Information Officer (CIO), Church Educational System, 2015 – Present.
Information Technology Vice President and CIO, Brigham Young University, 2002 – Present.
Associate Chair, Department of Computer Science, Brigham Young University, 2000 – 2002.
Graduate Coordinator, Department of Computer Science, Brigham Young University, 1999 – 2000.

ACADEMIC EXPERIENCE

Professor, Computer Science, Brigham Young University, 2004 – Present.
Associate Professor, Computer Science, Brigham Young University, 1999 – 2004.
Assistant Professor, Computer Science, Brigham Young, University, 1993 – 1999.
Visiting Professor and Researcher, High-Performance Computer Architecture Group, Intel Corporation, Hillsboro, Oregon, 1993 – 1994.
Instructor, High Performance Computer Architecture, Oregon State University, Corvallis, Oregon, 1994.

SERVICE

EXTERNAL

Founder and Chair, Internet of Things (IoT) Workshop, 2016 – Present.
Founder and Chair, University API (UAPI) Workshop, 2015 – Present.
Member, Academic Review Board for Computer and Information Sciences Department of Brigham Young University–Hawaii, 2015.
Member, Academic Review Board for Computer and Information Sciences Department of Brigham Young University–Hawaii, 2011.
Member, Utah Innovation Awards Devices Committee, 2016.
Chair, Utah Innovation Awards Devices Committee, 2015.
Reviewer, Numerous IEEE and ACM journals and conference proceedings.

UNIVERSITY

Member, President’s Council, 2002 – Present.
Chair, Information Technology Policy Committee (ITPC), 2002 – Present.
Member, BYU Online Committee, 2016 – Present.
Member, Academic Vice President Search Committee, 2010.
Chair, Information Technology Resources Committee (ITRC), 2000 – 2002.

COLLEGE

Chair, College of Physical and Mathematical Sciences Computing Committee, 2000 – 2002.

DEPARTMENT

 Member, Computer Science Faculty Search Committee, 2000 – 2002.
Chair, Computer Science Department Computing Committee, 1996 – 1999.
Member, Computer Science Department Computing Committee, 1993 – 1996.

COURSES TAUGHT

Book of Mormon, Rel 121, Brigham Young University, 2004.
Embedded Systems and Set Top Boxes, CS 598R, Brigham Young University, 2003.
Computer Organization, CS 143, Brigham Young University, 1998 – 2000.
Computer Architecture, CS 380, Brigham Young University, 1994 – 2000.
Advanced Computer Architecture, CS 580, Brigham Young University, 1995 – 2002.
Advanced Computer Architecture, ECE 570, Oregon State University, 1994.

PROFESSIONAL AFFILIATIONS

Association for Computing Machinery (ACM)
Institute of Electrical and Electronics Engineers (IEEE)
Special Interest Group on Computer Architecture (SIGARCH), ACM
Special Interest Group on Measurement and Evaluation (SIGMETRICS), ACM
EDUCAUSE

AWARDS AND HONORS

Golden Key Award, Utah Citizen of the Year, 2000.
Teacher of the Year, Department of Computer Science, BYU, 1998.
Honored Student Award, College of Engineering, BYU, 1988.

PATENTS

Flanagan et al. 2016. Systems and methods for secure intermediary data transfers using close proximity wireless communication. U.S. Patent 9,397,728, filed June 15, 2015, and granted July 19, 2016.

Flanagan et al. 2015. Systems and methods for establishing secure communication using close proximity wireless communication. U.S. Patent 9,088,864, filed October 3, 2013, and granted July 21, 2015.

Flanagan et al. 2015. Systems and methods for secure intermediary data transfers using close proximity wireless communication. U.S. Patent 9,084,078, filed October 3, 2013, and granted July 14, 2015.

RESEARCH FUNDING

A National Trace Collection and Distribution Resource, $1,529.978, National Science Foundation, 1998.
IA-32 Trace Collection and Workload Characterization, $42,500, Hewlett-Packard, 1998.
Performance Evaluation of Multiprocessor Architectures, $26,000, Hewlett-Packard,1998.
Performance Surface Analysis of Wide Area Distributed Systems, $150,000, Sprint Corporation, 1997.
Using ATM Networks for High Performance Computing, $100,000, Sprint Corporation, 1996.
Analysis of I/O Activity in Novell NetWare Clients and Server, $30,000, Intel Corporation. 1996.
Generating R4400 Instruction Traces, Tandem Corporation, $25,000, 1996.
Analysis of Disk Activity in A Novell NetWare Environment, Intel Corporation, $30,000, 1995.

PUBLICATIONS

JOURNALS

Clement, G. Judd, B. Morse, and K. Flanagan, Performance Surface Prediction for WAN-based Clusters, Journal of Supercomputing, Vol 13, 1999.

Flanagan, J. Archibald, and J. Su, Low Power Memory Hierarchies: An Argument for Second-Level Caches, Microprocessors and Microsystems, Vol 21, No. 5, February 1998.

Grimsrud, J. Archibald, M. Ripley, K. Flanagan, and B. Nelson, BACH: A Hardware Monitor for Tracing Microprocessor Based Systems, Microprocessors and Microsystems, Vol 17, No. 8, October 1993.

Li, B. Nelson, and K. Flanagan, CMOS Implementation of a Correlator for Delta-Modulated Signals, International Journal of Electronics, Vol 67, No. 2, 1989.

 CONFERENCE PROCEEDINGS

Myles G. Watson and Kelly Flanagan. “System-Level Prototyping with HyperTransport.” In Proceedings of the Second International Workshop for HyperTransport Research and Applications 2011 (WHTRA2011), Mannheim, Germany, February 2011.

Watson and J. K. Flanagan. “Designing Large Memories with Hardware Prototyping.” Workshop on Architectural Research Prototyping, Held in conjunction with ISCA, July 2006.

Myles G. Watson and J. Kelly Flanagan, Does Halting Make Trace Collection Inaccurate? A Case Study Using Pentium 4 Performance Counters and SPEC2000, In Proceedings of the Seventh IEEE Annual Workshop on Workload Characterization, October 2004.

Elizabeth S. Sorenson and J. Kelly Flanagan, Evaluating Synthetic Trace Models Using Locality Surfaces, Fifth Annual IEEE Workshop on Workload Characterization (WWC-5), Austin Texas, November 2, 2002, pp 23-33. 

Myles Watson and J. Kelly Flanagan. Simulating L3 Caches in Real Time Using Hardware Accelerated Cache Simulation (HACS): a Case Study with SPECint 2000, In Proc. 14th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Vitoria, ES, Brazil, October 2002, pp. 108-114. 

Elizabeth S. Sorenson and J. Kelly Flanagan, Cache Characterization Surfaces and Predicting Workload Miss Rates, Fourth Annual IEEE Workshop on Workload Characterization (WWC-4), Austin Texas, December 2, 2001.

Elizabeth S. Sorenson and J. Kelly Flanagan. Using Locality Surfaces to Characterize the SPECINT 2000 Benchmark Suite. In Lizy Kurian John and Ann Marie Grizzaffi Maynard, editors, Workload Characterization of Emerging Computer Applications, pages 101-120. Kluwer Academic Publishers, 2001.

Niki C. Thornock and J. Kelly Flanagan, Facilitating Level Three Cache Studies Using Set Sampling, Proceedings of the 2000 Winter Simulation Conference, Volume 1, pp 471-479. 

Niki C. Thornock and J. Kelly Flanagan, Using the BACH Trace Collection Mechanism to Characterize the SPEC 2000 Integer Benchmarks, Third Annual IEEE Workshop on Workload Characterization (WWC), Austin Texas, September 16, 2000.

Elizabeth S. Sorenson and J. Kelly Flanagan, Using Locality Surfaces to Characterize the SPECint 2000 Benchmark Suite, Third Annual IEEE Workshop on Workload Characterization (WWC), Austin Texas, September 16, 2000.

Jeff Penfold and J. Kelly Flanagan, A First Year Computer Organization Course on the Web: Make the Magic Disappear, IEEE Workshop on Computer Architecture Education (WCAE), Vancouver, BC, June 10, 2000.

Sorenson, E. Sorenson, K. Flanagan, H. Zhou, A System-Assisted Disk I/O Simulation Technique, IEEE International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS ’99), College Park, Maryland, October 24-28, 1999.

Peng, K. Flanagan, and F. Sorenson, Client-Based Web Prefetch Management, The Eighth International World Wide Web Conference, Toronto, Canada, May 11-14, 1999.

Flanagan and F. Sorenson, A National Trace Collection and Distribution Resource, 1999 SPEC Workshop, San Jose, California, January 25, 1999.

Judd, M. Clement, J. Peterson, B. Morse, and K. Flanagan, Performance Surface Prediction for WAN-Based Clusters, 31st Hawaii International Conference on System Sciences, Hawaii, January 6-9, 1998.

Thornock, X. Tu, and K. Flanagan, A Stochastic Disk I/O Simulation Technique, 1997 Winter Simulation Conference, Atlanta, December 7-10, 1997.

Clement, B. Morse, K. Flanagan, W. Wei and P. Crandall, The Chordal Spoke ATM Interconnection Network, Proceedings of the 1997 International Conference on Parallel and Distributed Techniques and Applications, Las Vegas, Nevada, June 1997.

Clement, K. Flanagan, and M. Steed, Cost Optimal Analysis for Workstation Clusters, Proceedings of the 1996 International Conference on Parallel and Distributed Processing Techniques and Applications, December, 1996.

Flanagan, B. Nelson, J. Archibald, and G. Thompson, The Inaccuracy of Trace-Driven Simulation Using Incomplete Multiprogramming Trace Data, IEEE International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, February 1996.

Thompson, B. Nelson, and K. Flanagan, Transaction Processing Workloads — A Comparison to the SPEC Benchmarks Using Memory Hierarchy Performance Studies, IEEE International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, February 1996.

Wei, M. Clement, and K. Flanagan, The Round Table ATM Interconnection Network, Proceedings of the 1995 International Conference on Parallel and Distributed Processing Techniques and Applications, November 1995.

Flanagan, B. Nelson, J. Archibald, and K. Grimsrud, Incomplete Trace Data and Trace Driven Simulation, IEEE International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, January 1993.

Grimsrud, J. Archibald, B. Nelson, and K. Flanagan, BACH: A Hardware Measurement Tool for Microprocessor Systems, Invited paper for IEEE Asilomar Conference, October 1992.

Flanagan, B. Nelson, J. Archibald, and K. Grimsrud, BACH: BYU Address Collection Hardware, The Collection of Complete Traces, In Proceedings of the 6th International Conference on Modeling Techniques and Tools for Computer Performance Evaluation, September 1992.

Nelson, J. Archibald, and K. Flanagan, Performance Analysis of Inclussion Effects in Multi-level Multiprocessor Caches, IEEE symposium on Parallel and Distributed Processing, December 1991.

Grimsrud and K. Flanagan, PARACHUTE: An Implementation of the Chordal Ring Architecture, Norddata 91, Norway, June 1991.

Flanagan, D. Morrell, R. Frost, C. Read, and B. Nelson, Vector Quantization Codebook Generation Using Simulated Annealing, IEEE International Conference on Acoustics, Speech, and Signal Processing, May 1989.

Read, D. Chabries, R. Christansen, and K. Flanagan, A Method for Computing the DFT of Vector Quantized Data, IEEE International Conference on Acoustics, Speech, and Signal Processing, May 1989.

Flanagan and B. Nelson, Microprocessor Design Using Path Programmable Logic, IEEE International Conference on Computer Design / VLSI in Computers, October 1988.

Li, B. Nelson, K. Flanagan, and C. Read, A Multiprogrammed Parallel Architecture fir Digital Signal Processing, IEEE International Conference on Acoustics, Speech, and Signal Processing, April 1987.

OTHER PUBLICATIONS

Niki C. Thornock and J. Kelly Flanagan, A National Trace Collection and Distribution Resource, ACM SIGARCH Computer Architecture News, June 2001, Volume 29, Issue 3.

Elizabeth S. Sorenson and J. Kelly Flanagan, Using locality surfaces to characterize the SPECint 2000 benchmark suite, Workload Characterization for Emerging Computer Applications, pages 101-120, Kluwer Academic Publishers, 2001.

Rose and K. Flanagan, Complete Instruction Traces from Incomplete Address Traces (CITCAT), Poster Presentation, 1997 Winter Simulation Conference, Atlanta, December 7-10, 1997.

Rose and K. Flanagan, Complete Instruction Traces from Incomplete Address Traces (CITCAT), Computer Architecture News, December 1996.

PRESENTATIONS

University API Workshop, 2016.
Indie Educational Technology Workshop, 2016.
Internet Identity Workshop, 2015.
InfoWorld Virtualization Executive Forum, 2007.
InfoWorld Virtualization Executive Forum, 2006.
Keynote, BYU Accessibility Banquet, 2006.
BYU Devotional Address, 2002.
Numerous BYU presentations, 2002 – Present.
Numerous presentations at Hewlett-Packard, Intel, Texas Instruments, and Tandem, 1995 – 2000.

THESES AND DISSERTATIONS SUPERVISED

Steven C. Cook, Dynamic Near Field Communication Pairing, 2013, Thesis.
Elizabeth S. Sorenson, Cache Characterization and Performance Studies Using Locality Surfaces, 2005, Dissertation.
Christopher R. Slade, On-Disk Sequence Cache (ODSC): Using Excess Disk Capacity to Increase Performance, 2005, Thesis.
Myles G. Watson, Does the Halting Necessary for Hardware Trace Collection Inordinately Perturb the Results?, 2004, Thesis.
Hyrum Carroll, A Trace-Driven Simulator for Palm OS Devices, 2004, Thesis.
Franklin E. Sorenson, PODS: Physical Object Devices, 2004, Thesis.
Vernon H. Mauery, Inheritance Models in Object-Oriented Hardware Using Physical Object Devices, 2004, Thesis.
Darren Hart, Using Hardware Objects in Object Oriented Software Design, 2004, Thesis.
Briton Barker, Cache Memory Analysis: Effects of the Kernel and the Justification of Associativity, 2001, Thesis.
Elizabeth S. Sorenson, Locality Surfaces, 2001, Thesis.
Alen Peacock, Dynamic Detection of Deterministic Disk Access Patterns, 2001, Thesis.
Dong Lin, Reducing Energy Consumption using Disk Data Reorganization, 2000, Thesis.
Niki Thornock, Using Set Sampling for Level Three Cache Studies, 1999, Thesis.
Charlton Rose, CITCAT: Complete Instruction Traces from Cache Filtered Address Traces, 1999, Thesis.
Song Peng, Client-Based Web Prefetch Management, 1998, Thesis.
YiQiang Huang, Reducing WWW Latency Using Server-Based Prefetching Techniques, 1998, Thesis.
Heng Zhou, A System-Assisted Disk I/O Simulation Technique, 1998, Thesis.
Nianlong Yin, Reducing Application Load Time by Rearranging Disk Data, 1998, Thesis.
Chulkee Sung, A Markov Model for Novell Netware Network Traffic, 1997, Thesis.
Xiao-hong Tu, Disk Rearrangement on Novell Netware Systems, 1997, Thesis.
Jun Su, Cache Optimization for Energy Efficient Memory Hierarchies, 1996, Thesis.